1. Field of the Invention
The present invention relates to a memory cell and its method of manufacture and more particularly, to a dynamic random access memory (hereinafter DRAM) cell having an isolation merged trench for applying to 16 megabit and 64 megabit DRAM cells.
2. Description of the Prior Art
Various types of semiconductor memory devices are well known in the art. In such known semiconductor memory devices, it is a present situation that 1 megabit DRAMs are being mass produced, 4 megabit DRAMs and 16 megabit DRAMs are being developed in pilot productions, and 64 megabit DRAMs are also being developed successively.
In order to develop such large quantity memory devices, fundamental techniques such as lithographic techniques or thin film forming techniques must be developed in addition to developing the DRAM cell as a fundamental element of the DRAM structure.
The DRAM cell has been subjected to many changes from a plane structure to a trench or a stack structure, and the DRAM cell is being developed to maximize the area efficiency as far as possible under a condition that its method of manufacture is allowed.
That is, a high density DRAM cell has been changed from a system for forming a storing capacitor on a plane form so as to reduce the cell area to a system for forming a merged capacitor utilizing a trench as a solid form as well as a stack type capacitor as a system for stacking multiple layers of polysilicon. Presently among such systems, the isolation merged trench structure for surrounding the active region by the trench capacitor has been disclosed as a kind of suitable structure for applying to the DRAM cell to more than 16 megabit or 64 megabit memories.
FIG. 1 and FIG. 2 are sectional views of typical conventional isolation merged trench capacitors showing an isolation merged vertical capacitor cell (hereinafter IVEC) and a surrounded capacitor cell (hereinafter SCC).
The IVEC as shown in FIG. 1 is disclosed by Nippon Telegraph and Telephone Public Corporation of Japan and is related to 4M and 16M DRAM cells. The IVEC is made in such a manner that an isolation region of a switching transistor is utilized as a charge storing capacitor so that the area efficiency of the cell is excellent.
In FIG. 1, reference numeral 1 represents a silicon substrate, numeral 2 is a capacitor dielectric film, numbers 3 and 6 are n.sup.+ doped polysilicon regions, numeral 4 is an n.sup.+ diffusion layer, numerals 5, 7 and 9 are silicon oxide films, and numeral 8 represents an aluminum metal wiring, respectively. The charge storage of this cell is provided between the first polysilicon 3 of a storing electrode of a trench interior and a second polysilicon 3A of a plate electrode.
In FIG. 2, reference numeral 10 represents a silicon substrate, numeral 11 is a p.sup.+ diffusion layer, numerals 12 and 20 are n.sup.+ diffusion layers, numeral 13 is a capacitor dielectric film, numerals 14, 17, 18 and 19 are silicon oxide films, numeral 15 is an n.sup.+ doped polysilicon region, numeral 16 is an aluminum metal wiring, and numeral 21 represents a polysilicon region, respectively. The isolation region of the switching transistor is utilized as a charge storing capacitor. The charge storage is made by using the n.sup.+ diffusion layer 12 doped to the interior wall surface of the trench as a storing electrode and the polysilicon 21 filled within the trench as a plate electrode.
However, such conventional isolation merged trench capacitors have a Hi-C (high capacitance) structure. The Hi-C structure has not only disadvantages of alpha particles, but also disadvantages of a punch-through phenomenon which includes leakage current from the surface between the trenches and the bulk region.
In order to solve such problems, an impurity concentration of the p-substrate or the p-well should be raised for maintaining a value less than a leakage current of pA.
When the impurity concentration of the p-substrate becomes too high, the breakdown voltage is lowered and also various problems such as a body effect of n-MOSFET, a sub-threshold swing, a threshold voltage control becomes apparent. Therefore, in order to overcome such problems, because the required distance between capacitors is determined to be approximately 1.5 .mu.m as a minimum, it has reached the limit for reducing the unit cell. Because all IVEC and SCC structures utilize a capacitor including one surface as the storing electrode and one surface as the plate electrode, there is a disadvantage that the area efficiency is reduced when used as a highly integrated cell.